// ****************************************************************************** 
// Copyright     :  Copyright (C) 2018, Hisilicon Technologies Co. Ltd.
// File name     :  glb_cfg_vclk_reg_offset.h
// Project line  :  K3
// Department    :  K3
// Author        :  Huawei
// Version       :  V100
// Date          :  2015/4/10
// Description   :  HiVcodecV100 VDEC
// Others        :  Generated automatically by nManager V4.2 
// History       :  Huawei 2018/04/10 10:02:43 Create file
// ******************************************************************************

#ifndef __GLB_CFG_VCLK_REG_OFFSET_H__
#define __GLB_CFG_VCLK_REG_OFFSET_H__

/* GLB_CFG_VCLK Base address of Module's Register */
#define SOC_GLB_CFG_VCLK_BASE                       (0xc000)

/******************************************************************************/
/*                      SOC GLB_CFG_VCLK Registers' Definitions                            */
/******************************************************************************/

#define SOC_GLB_CFG_VCLK_AVS_PLUS_REG          (SOC_GLB_CFG_VCLK_BASE + 0x0)  
#define SOC_GLB_CFG_VCLK_EMAR_ADDR_REG         (SOC_GLB_CFG_VCLK_BASE + 0x4)  
#define SOC_GLB_CFG_VCLK_VDH_RST_EN_REG        (SOC_GLB_CFG_VCLK_BASE + 0x8)  
#define SOC_GLB_CFG_VCLK_CK_GT_EN_REG          (SOC_GLB_CFG_VCLK_BASE + 0xC)  
#define SOC_GLB_CFG_VCLK_VDH_USE_STATE_REG     (SOC_GLB_CFG_VCLK_BASE + 0x10) 
#define SOC_GLB_CFG_VCLK_OVER_TIME_REG         (SOC_GLB_CFG_VCLK_BASE + 0x18) 
#define SOC_GLB_CFG_VCLK_VDH_ARQOS_REG         (SOC_GLB_CFG_VCLK_BASE + 0x24) 
#define SOC_GLB_CFG_VCLK_VDH_ARQOS_CYCLE_REG   (SOC_GLB_CFG_VCLK_BASE + 0x28) 
#define SOC_GLB_CFG_VCLK_VDH_ARQOS_NUMBERS_REG (SOC_GLB_CFG_VCLK_BASE + 0x2C) 
#define SOC_GLB_CFG_VCLK_EMAR_ADDR1_REG        (SOC_GLB_CFG_VCLK_BASE + 0x30) 
#define SOC_GLB_CFG_VCLK_VDH_FORCE_REQ_ACK_REG (SOC_GLB_CFG_VCLK_BASE + 0x34) 
#define SOC_GLB_CFG_VCLK_VDH_RFS_RAS_EMA_REG   (SOC_GLB_CFG_VCLK_BASE + 0x70) 
#define SOC_GLB_CFG_VCLK_VDH_RFT_EMA_REG       (SOC_GLB_CFG_VCLK_BASE + 0x74) 
#define SOC_GLB_CFG_VCLK_VDH_ROM_EMA_REG       (SOC_GLB_CFG_VCLK_BASE + 0x78) 
#define SOC_GLB_CFG_VCLK_VDH_MEM_ECC_REG       (SOC_GLB_CFG_VCLK_BASE + 0x7C) 

#endif // __GLB_CFG_VCLK_REG_OFFSET_H__
